open GPU interconnect standard
UALink consortium hits 100+ members, releases v2.0 spec to challenge NVLink in GPU scale-up Open Compute ProjectTL;DW
- UALink is an open industry standard backed by 100+ companies to provide scale-up fabric competition against Nvidia's proprietary NVLink.
- Scale-up fabrics must enable direct memory access via reads/writes, not data movement—if you're moving data, you're doing scale-out, not scale-up.
- UALink supports 800 gigabits per second bandwidth with configurable 400 Gbps or 200 Gbps lanes; designed for small packet efficiency typical of memory accesses.
- Training workloads prioritize bandwidth; inference prioritizes latency—choose fabric based on your specific AI workload requirements.
- UALink 2.0 spec includes in-network collectives (INK), management specs, and chiplet specs; products from 1.0 spec expected end of 2024/early 2025.
- Ethernet cannot match NVLink performance: UALink maintains high efficiency (vs. Ethernet's 60%) for mixture-of-experts models requiring GPU-to-GPU communication.
- Multiple switch vendors (Marvell, Astera Labs) and accelerator vendors (AMD, Intel) designing UALink solutions; creates competitive ecosystem versus single-vendor lock-in.
- Interconnect choice is strategic and long-term—incorrect decisions create lasting constraints; evaluate architecture carefully before deployment.
- UALink uses standard Ethernet physical layer (802.3), enabling reuse of existing cables, re-timers, and management infrastructure.
TL;DW
- UALink is an open industry standard backed by 100+ companies to provide scale-up fabric competition against Nvidia's proprietary NVLink.
- Scale-up fabrics must enable direct memory access via reads/writes, not data movement—if you're moving data, you're doing scale-out, not scale-up.
- UALink supports 800 gigabits per second bandwidth with configurable 400 Gbps or 200 Gbps lanes; designed for small packet efficiency typical of memory accesses.
- Training workloads prioritize bandwidth; inference prioritizes latency—choose fabric based on your specific AI workload requirements.
- UALink 2.0 spec includes in-network collectives (INK), management specs, and chiplet specs; products from 1.0 spec expected end of 2024/early 2025.
- Ethernet cannot match NVLink performance: UALink maintains high efficiency (vs. Ethernet's 60%) for mixture-of-experts models requiring GPU-to-GPU communication.
- Multiple switch vendors (Marvell, Astera Labs) and accelerator vendors (AMD, Intel) designing UALink solutions; creates competitive ecosystem versus single-vendor lock-in.
- Interconnect choice is strategic and long-term—incorrect decisions create lasting constraints; evaluate architecture carefully before deployment.
- UALink uses standard Ethernet physical layer (802.3), enabling reuse of existing cables, re-timers, and management infrastructure.
Curtis Bowman walks through UALink's 800 Gbps-per-lane, memory-semantic fabric targeting tight accelerator coupling as a single logical memory space—PCIe latency at Ethernet bandwidth. v2.0 adds in-network collectives, management, and chiplet specs; AMD, Marvell, and Astera Labs are building compatible silicon.